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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91CW12A
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0 to 4, INTRTC) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP91CW12A
CMOS 16-Bit Microcontrollers
TMP91CW12AF 1. Outline and Features
TMP91CW12AF is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91CW12AF comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (1.0 s/2 bytes at 16 MHz) (2) Minimum instruction execution time: 148 ns (at 27 MHz) (3) Built-in RAM: 4 Kbytes Built-in ROM: 128 Kbytes (4) External memory expansion Expandable up to 16 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus * * * Dynamic data bus sizing (5) 8-bit timers: 8 channels (6) 16-bit timer/event counter: 2 channels (7) General-purpose serial interface: 2 channels UART/Synchronous mode: 2 channels IrDA ver 1.0 (115.2 kbps) supported: 1 channel
030519EBP1
The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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(8) Serial bus interface: 1 channel I2C bus mode/clock synchronous select mode (9) 10-bit AD converter (sample-hold circuit is built in): 8 channels (10) Watchdog timer (11) Timer for real-time clock (RTC) (12) Chip Select/Wait controller: 4 channels (13) Interrupts: 45 interrupts 9 CPU interrupts: Software interrupt instruction and illegal instruction 26 internal interrupts: 7-level priority can be set. 10 external interrupts: 7-level priority can be set. (14) Input/output ports: 81 pins (15) Standby function Three Halt modes: Idle2 (programmable), Idle1, Stop (16) Triple-clock controller Clock Doubler (DFM) Clock Gear (fc to fc/16) Slow mode (fs (17) Operating voltage VCC VCC (18) Package 100-pin QFP: P-LQFP100-1414-0.50F 2.7 V to 3.6 V (fc max 1.8 V to 3.6 V (fc max 27 MHz) 10 MHz) 32.768 kHz)
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DVCC [3] DVSS [3] X1 X2 EMU0 EMU1 XT1 (P96) XT2 (P97)
RESET
ADTRG (P53) AN0 to AN7 (P50 to P57)
CPU (TLCS-900/L1)
AVCC, AVSS VREFH, VREFL TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) TXD1 (P93) RXD1 (P94) SCLK1/ CTS1 (P95) SCK (P60) SO/SDA (P61) SI / SCL (P62)
10-Bit 8CH AD Converter
SIO/UART/IrDA
XWA XBC XDE XHL XIX XIY XIZ XSP
(SIO0) SIO/UART (SIO1) Serial Bus Interface (SBI) 8-Bit Timer (TMRA0) 8-Bit Timer (TMRA1) 8-Bit Timer (TMRA2)
WA BC DE HL IX IY IZ SP 32 bits SR F PC C Watch-Dog Timer (WDT) Real-Clock Timer (RTC)
H-OSC Clock Gear Clock doubler L-OSC
AM0 AM1 ALE Port 0 Port 1 Port 2 (P00 to P07) AD0 to AD7 (P10 to P17) AD8/A8 to AD15/A15 (P20 to P27) A0/A16 to A7/A23 RD (P30) WR (P31) HWR (P32) BUSRQ (P34) BUSAK (P35) R/ W (P36) P37 (P64) SCOUT, P65, P66 PA4 to PA7 (P40 to P43) CS0 to CS3
WAIT (P33)
TA0IN (P70) TA1OUT (P71)
Port 3
Port 6 Port A
CS/WAIT
TA3OUT (P72)
8-Bit Timer (TMRA3) 4-KB RAM 8-Bit Timer (TMRA4) 8-Bit Timer (TMRA5) 8-Bit Timer (TMRA6) 128-KB ROM
TA4IN (P73) TA5OUT (P74)
Controller (4-BLOCK) Interrupt Controller
16-Bit Timer (TMRB0) 16-Bit Timer (TMRB1)
TA7OUT (P75)
8-Bit Timer (TMRA7)
NMI INT0 (P63) INT1 to 4 (PA0 to 3) TB0IN0/INT5 (P80) TB0IN1/INT6 (P81) TB0OUT0 (P82) TB0OUT1 (P83) TB1IN0/INT7 (P84) TB1IN1/INT8 (P85) TB1OUT0 (P86) TB1OUT1 (P87)
(
): Initial function after reset
Figure 1.1 TMP91CW12AF Block Diagram
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2.
Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91CW12AF, their names and functions are as follows:
2.1
Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91CW12AF.
88 P65 DVCC P66 DVSS P50/AN0 P51/AN1 P52/AN2 89 90 91 92 93 94 87 P64/SCOUT 86 P63/INT0 85 P62/SI/SCL 84 P61/SO/SDA 83 P60/SCK 82 P43/CS3 81 P42/CS2 80 P41/CS1 79 P40/CS0 78 P37 77 P36/R/W 76 P35/BUSAK 75 P34/BUSRQ 74 P33/WAIT 73 P32/HWR 72 P31/WR 71 P30/RD 70 P27/A7/A23 69 P26/A6/A22 68 P25/A5/A21 67 P24/A4/A20 66 P23/A3/A19 65 P22/A2/A18
P53/AN3/ADTRG 95 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/TA7OUT 96 97 98 99
100
1 2 3 4 5 6 7 8 9
P80/TB0IN0/INT5 10 P81/TB0IN1/INT6 11 P82/TB0OUT0 P83/TB0OUT1 12 13
Top View LQFP100
64 DVCC 63 NMI 62 DVSS 61 P21/A1/A17 60 P20/A0/A16 59 P17/AD15/A15 58 P16/AD14/A14 57 P15/AD13/A13 56 P14/AD12/A12 55 P13/AD11/A11 54 P12/AD10/A10 53 P11/AD9/A9 52 P10/AD8/A8 51 P07/AD7 50 P06/AD6 49 P05/AD5 48 P04/AD4 47 P03/AD3 46 P02/AD2 45 P01/AD1 44 P00/AD0 43 ALE 42 PA7 41 PA6 40 PA5 39 PA4 38 PA3/INT4
P84/TB1IN0/INT7 14 P85/TB1IN1/INT8 15 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P93/TXD1 P94/RX1 16 17 18 19 21 22
P92/SCLK0/CTS0 20
P95/SCLK1/CTS1 23 AM0 DVCC X2 DVSS X1 AM1 RESET P96/XT1 P97/XT2 EMU0 EMU1 PA0/INT1 PA1/INT2 PA2/INT3 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Figure 2.1.1 Pin assignment diagram (100-pin LQFP)
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2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions. Table 2.2.1 Pin Names and Functions (1/3)
Pin Name
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of Pins
8 8
I/O
I/O Tri-state I/O Tri-state Output I/O Output Output Output Output Output Output I/O Output I/O Input I/O Input I/O Output I/O Output I/O I/O Output I/O Output I/O Output I/O Output Input Input Input I/O I/O I/O Output I/O I/O Input I/O I/O Input I/O Output
Functions
Port 0: I/O port that allows I/O to be selected at the bit level Address and data (lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 34: I/O port (with pull-up resistor) Bus Request: Signal used to request Bus Release Port 35: I/O port (with pull-up resistor) Bus Acknowledge: Signal used to acknowledge Bus Release Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 37: I/O port (with pull-up resistor) Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 if address is within specified address area Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 if address is within specified address area Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 if address is within specified address area Port 5: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD converter Port 60: I/O port Serial bus interface clock in SIO Mode Port 61: I/O port Serial bus interface output data in SIO Mode Serial bus interface data in I2C bus Mode Port 62: I/O port Serial bus interface input data in SIO Mode Serial bus interface clock in I2C bus Mode Port 63: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge Port 64: I/O port System Clock Output: Outputs fFPH or fs clock.
8
1 1 1 1 1 1 1 1 1
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
P36 R/ W P37 P40
CS0
P41
CS1
1 1 1 8
P42
CS2
P43
CS3
P50 to P57 AN0 to AN7
ADTRG
P60 SCK P61 SO SDA P62 SI SCL P63 INT0 P64 SCOUT
1 1
1
1
1
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Table 2.2.1 Pin Names and Functions (2/3) Pin Name
P65 P66 P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P75 TA7OUT P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 TXD0 P91 RXD0 P92 SCLK0
CTS0
Number of Pins
1 1 1 1 1 1 1 1 1
I/O
I/O I/O I/O Input I/O Output I/O Output I/O Input I/O Output I/O Output I/O Input Input Port 65: I/O port Port 66: I/O port Port 70: I/O port Timer A0 Input Port 71: I/O port Timer A1 Output Port 72: I/O port Timer A3 Output Port 73: I/O port Timer A4 Input Port 74: I/O port Timer A5 Output Port 75: I/O port Timer A7 Output
Functions
Port 80: I/O port Timer B0 Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. Port 81: I/O port Timer B0 Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port Timer B0 Output 0 Port 83: I/O port Timer B0 Output 1 Port 84: I/O port Timer B1 Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port Timer B1 Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port Timer B1 Output 0 Port 87: I/O port Timer B1 Output 1 Port 90: I/O port Serial Send Data 0 (Programmable open-drain) Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 (Programmable open-drain) Port 94: I/O port (with pull-up resistor) Serial Receive Data 1 Port 95: I/O port (with pull-up resistor) Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port (Open-drain output) Low-frequency oscillator connection pin
1
I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input I/O Input
1 1 1
1
1 1 1 1 1
P93 TXD1 P94 RXD1 P95 SCLK1
CTS1
1 1 1
P96 XT1
1
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Table 2.2.1 Pin Names and Functions (3/3) Pin Name
P97 XT2 PA0 to PA3 INT1 to INT4 PA4 to PA7 ALE
NMI
Number of Pins
1 4
I/O
I/O Output I/O Input I/O Output Input Input Output Input Input Input I/O
Functions
Port 97: I/O port (Open-drain output) Low-frequency oscillator connection pin Ports A0 to A3: I/O ports Interrupt Request Pins 1 to 4: Interrupt request pins with programmable rising edge / falling edge. Ports A4 to A7: I/O ports Address Latch Enable Can be disabled to reduce noise. Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both edge. Address Mode: The Vcc pin should be connected. Test Pins: Open pins Reset: initializes TMP91CW12A. (With pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) High-frequency oscillator connection pins Power supply pin for AD converter GND pin for AD converter (0 V) Power supply pins (All VCC pins should be connected with the power supply pin.) GND pins (0 V) (All VSS pins should be connected with the power supply pin.)
4 1 1 2 1 1 1 1 1 1 2 3 3
AM0 to 1 EMU0/EMU1
RESET
VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS
Note: An external DMA controller cannot access the device's built-in memory or built-in I/O devices using the BUSRQ and BUSAK signal.
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3.
Operation
This section describes the basic components, functions and operation of the TMP91CW12AF.
3.1 CPU
The TMP91CW12AF incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a description of this CPU's operation, please refer to the section of this data book which describes the TLCS-900/L1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP91CW12AF; these functions are not covered in the section devoted to the TLCS-900/L1 CPU.
3.1.1
Reset
When resetting the TMP91CW12AF microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 10 system clocks (ten states: 80 s at 4 MHz). When the Reset has been accepted, the CPU performs the following: Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored at address FFFF00H to FFFF02H: PC<0 to 7> PC<8 to 15> PC<16 to 23> Data in location FFFF00H Data in location FFFF01H Data in location FFFF02H
Sets the Stack Pointer (XSP) to 100H. Sets bits of the Status Register (SR) to 111 (thereby setting the Interrupt Level Mask Register to level 7). Sets the bit of the Status Register to 1 (MAX Mode). Clears bits of the Status Register to 000 (thereby selecting Register Bank 0). When the Reset is cleared, the CPU starts executing instructions according to the Program Counter settings. CPU internal registers not mentioned above do not change when the Reset is cleared. When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows. Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to General-Purpose Input or Output Port Mode. Sets the ALE pin to High-Z.
Note 1: Except PC,SR and XSP register of CPU and data of internal RAM are not change by reset operation.
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3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP91CW12AF.
000000H
Internal I/O (4 Kbytes)
Direct area (n)
000100H 001000H Internal RAM (4 Kbytes) 002000H
64-Kbyte area (nn)
010000H
External memory
FE0000H
Internal ROM (128 Kbytes)
16-Mbyte area (R) ( R) (R ) (R R8/16) (R d8/16) (nnn)
FFFF00H FFFFFFH
Vector Table (256 Bytes) ( Internal area)
Figure 3.2.1 Memory Map
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3.3 Differences Between TMP91CW12AF and TMP91CW12F
(1) Outline TMP91CW12AF is a high-speed and low-voltage products of TMP91CW12F. The specification of function is added following item to TMP91CW12F. The major difference points of A, C and D, C characteristics are operation voltage (CW12F: 5 V/3 V, CW12AF: 3 V/2 V) and Fmax (CW12F: 16 MHz, CW12AF:27 MHz) at 3 V. For the details, please refer to 4.Electrical Characteristics. (2) Differences of Function
3.3.1
CS/WAIT controller
Wait operation setting is added in order to high-speed of operation frequency on TMP91CW12AF. It is explained at Table 3.3.1. Figure 3.3.1 shows SFR setting. Table 3.3.1 Wait operation settings
No. of Waits
000 001 010 2 waits 1 wait 1 wait N
Wait Operation
Inserts a wait of two states, irrespective of the WAIT pin state. Inserts a wait of one state, irrespective of the WAIT pin state. Inserts one wait state, then continuously samples the state of the WAIT pin. While the WAIT pin remains Low, the wait continues; the the bus cycle is prolonged until the pin goes High. Ends the bus cycle without a wait, regardless of the WAIT pin state. Don't setting Inserts a wait of three states, irrespective of the WAIT pin state. Inserts a wait of four states, irrespective of the WAIT pin state. Inserts a wait of eight states, irrespective of the WAIT pin state.
011 100 101 110 111
0 waits Reserved 3 waits 4 waits 8 waits
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Chip Select/Wait Control Register 7
B0CS (00C0H)
ReadModifyWrite instructions are prohibited.
6
5
B0OM1 0
4
B0OM0 0
3
B0BUS W 0
Data bus width 0: 16 bits 1: 8 bits
2
B0W2 0
Number of Waits 000: 2 waits 001: 1 wait 010: 1 wait N 011: 0 waits
1
B0W1 0
100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits
0
B0W0 0
Bit symbol Read/Write After reset Function
B0E W 0
Chip Select Set up 0: Disable 1: Enable
Chip Select output waveform selection 00: For ROM/SRAM 01: 10: Reserved 11:
B1CS (00C1H)
ReadModifyWrite instructions are prohibited.
Bit symbol Read/Write After reset Function
B1E W 0
Chip Select Set up 0: Disable 1: Enable
B1OM1 0
B1OM0 0
B1BUS W 0
Data bus width 0: 16 bits 1: 8 bits
B1W2 0
Number of Waits 000: 2 waits 001: 1 wait 010: 1 wait N 011: 0 waits
B1W1 0
B1W0 0
Chip Select output waveform selection 00: For ROM/SRAM 01: 10: Reserved 11:
100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits
B2CS (00C2H)
ReadModifyWrite instructions are prohibited.
Bit symbol Read/Write After reset Functions
B2E 1
Chip Select Set up 0: Disable 1: Enable
B2M 0
CS2 area selection 0: 16-Mbyte area 1: CS area
B2OM1 0
B2OM0 W 0
B2BUS 0
Data bus width 0: 16 bits 1: 8 bits
B2W2 0
Number of waits 000: 2 waits 001: 1 wait 010: 1 wait N 011: 0 waits
B2W1 0
B2W0 0
Chip Select output waveform selection 00: For ROM/SRAM 01: 10: Reserved 11:
100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits
B3CS (00C3H)
ReadModifyWrite instructions are prohibited.
Bit symbol Read/Write After reset Function
B3E W 0
Chip Select Set up 0: Disable 1: Enable
B3OM1 0
B3OM0 0
B3BUS W 0
Data bus width 0: 16 bits 1: 8 bits
B3W2 0
Number of waits 000: 2 waits 001: 1 wait 010: 1 wait N 011: 0 waits
B3W1 0
B3W0 0
Chip Select output waveform selection 00: For ROM/SRAM 01: 10: Reserved 11:
100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits
BEXCS (00C7H)
ReadModifyWrite instructions are prohibited.
Bit symbol Read/Write After reset Function
BEXBUS 0
Data bus width 0: 16 bits 1: 8 bits
BEXW2 0 0
BEXW1 0
BEXW0 0
Number of Waits 000: 2 waits 001: 1 waits 010: 1 wait N 011: 0 waits
100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits
Master enable bit
Chip select output waveform selection
0 1
Prohibit Permission
Number of address area waits (See 3.3.1 Wait Control.)
00 For ROM/SRAM 01 10 11
Reserved
CS2 area selection 0 1 16-Mbyte area Specified address area
Data bus width selection
0 1
16-bit data bus 8-bit data bus
Figure 3.3.1 Chip Select/Wait Control Registers
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TMP91CW12A 3.3.2 IrDA function
The SIRCR register is added. This register can be the selection the logic of recieving data from external IrDA module. Figure 3.3.3 shows SFR setting.
Received pulse

Received pulse
0

1
start 1 0 0 1 0 1 1 0 stop
Data after Demodulation
Figure 3.3.2 Demodulation of Received data
7
SIRCR (0207H) Bit symbol Read/Write After reset Function 0
Select transmit pulse width 0: 3/16 1: 1/16
6
RXSEL 0
Received Data 0: H pulse 1: L
5
TXEN 0
Transmit 0: disable 1: enable
4
RXEN 0
Receive 0: disable 1: enable
3
SIRWD3 R/W 0
2
SIRWD2 0
1
SIRWD1 0
0
SIRWD0 0
x
PLSEL
Select receive pulse width Set effective pulse width for equal or more than 2x (value 1) Values in the range 1 to 14 can be set
Select receive pulse width Formula: Effective pulse width x 1/fFPH 0000 0001 to 1110 1111 Equal or more than 30x Can not be set Cannot be set Equal or more than 4x
2x
x (value
1)
100 ns 100 ns
Receive operation 0 1 Disabled Enabled
Transmit operation 0 1 Disabled Enabled
Select transmit pulse width 0 1 3/16 1/16
Note: When the baud rate is slow and the IrDA1.0specified pulse width (minimum: 1.6 s) can be secured, setting this bit to 1 enables infrared light-up time to be decreased reducing power consumption.
Figure 3.3.3 IrDA Control Register
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TMP91CW12A 3.3.3 Clock Doubler (DFM) function
Input frequency range to DFM (frequency of high-frequency oscillator) is different from TMP91CW12. Therefore, the DFMCR1 register is added to select frequency-range. (DFMCR1 register don't exist in TMP91CW12) Write the following data according to the operating condition before starting lock-up.
7
DFMCR1 (00E9H) Bit symbol Read/Write After reset Function 0
6
5
4
R/W
3
2
1
0
0
0
1
0
0
1
1
Write 0BH when the fOSCH Write 1BH when the fOSCH
4 to 6.75 MHz at Vcc = 3 V 10% 2 to 2.5 MHz at Vcc = 2 V 10%
Figure 3.3.4 DFM Control Register 1
3.3.4
Others
(1) Limitation of selecting drivability of High-frequency oscillator The case of VCC 2.0 V 10%, it is impossible to use selecting function of drivability of High-frequency oscillator. Do not write 0 to EMCCR0.
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4.
Electrical Characteristics
4.1 Absolute Maximum Ratings
Parameter
Power Supply Voltage Input Voltage Output Current Output Current Output Current (total) Output Current (total) Power Dissipation (Ta 85C)
Symbol
Vcc VIN IOL IOH IOL IOH PD TSOLDER TSTG TOPR
Rating
0.5 to 4.0 0.5 to Vcc 2 2 80 80 600 260 65 to 150 40 to 85 0.5
Unit
V V mA mA mA mA mW C C C
Soldering Temperature (10 s) Storage Temperature Operating Temperature
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
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4.2 DC Characteristics (1/2)
Typ. (Note1)
Parameter
Power Supply Voltage (AVcc DVcc) (AVss DVss 0 V)
Symbol
fc VCC fc VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH
Condition
4 to 27 MHz 2 to 10 MHz 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 1.6mA 0.4mA 400 A 200 A Vcc Vcc Vcc Vcc 2.7 V 2.7 V 2.7 V 2.7 V fs 30 to 34 kHz
Min
2.7
Max
Unit
3.6 1.8 0.6 0.2 Vcc 0.3 Vcc 0.2 Vcc 0.3 0.25 Vcc 0.15 Vcc 0.3 0.3 0.2 Vcc 0.1 Vcc 2.0 0.7 Vcc 0.7 Vcc 0.8 Vcc 0.75 Vcc 0.85 Vcc Vcc 0.3 Vcc 0.3 0.8 Vcc 0.9 Vcc 0.45 0.15 Vcc 2.4 0.8 Vcc Vcc 0.3
V
P00 to P17 (AD0 to 15) P20 to PA7 (except P63)
RESET , NMI , P63 (INT0)
Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc IOL IOL IOH IOH
Input Low Voltage
AM0, 1 X1 P00 to P17 (AD0 to 15) P20 to PA7 (except P63)
RESET , NMI , P63 (INT0)
V
Input High Voltage
AM0, 1 X1
Output Low Voltage Output High Voltage
V
Note1: Typical values are for when Ta
25C and Vcc
3.0 V unless otherwise noted.
91CW12A-15
2003-05-21
TMP91CW12A
4.2 DC Characteristics (2/2)
Typ. (Note1)
0.02 0.2 1.8 100 200 0.4 0.3 10% 10% 100 200 7.0 2.5 1.0 1.7 0.6 0.25 11.6 5.2 3.0 7.7 3.5 2.0 0.1 1.0 0.8 400 1000 10.0 3.5 1.8 2.5 0.9 0.4 30 19 8 15 20 13 10 10 A A A mA mA 0.05
Parameter
Input Leakage Current Output Leakage Current Power Down Voltage (at STOP, RAM back-up)
RESET Pull-up Resistor
Symbol
ILI ILO VSTOP RRST CIO VTH RKH Icc 0.0 0.2
Condition
VIN VIN Vcc Vcc
Min
Max
5 10 3.6 400 1000 10
Unit
A V K PF V K
V IL2 0.2 Vcc, V IH2 0.8 Vcc Vcc Vcc fc Vcc Vcc Vcc 3V 2V 1 MHz 2.7 V 3V 2V 10% 10%
Pin Capacitance Schmitt Width RESET , NMI , INT0 Programmable Pull-up Resistor Normal (Note 2) Idle2 Idle1 Normal (Note 2) Idle2 Idle1 Slow (Note 2) Idle2 Idle1 Slow (Note 2) Idle2 Idle1 Stop
Vcc < 2.7 V
Vcc 3 V 10% fc 27 MHz Vcc 2 V 10% fc 10 MHz (Typ.: Vcc 2.0 V) Vcc 3 V 10% fs 32.768 kHz Ta Ta 70C 85C
Vcc 2 V 10% fs 32.768 kHz (Typ.: Vcc 2.0 V) Vcc 1.8 to 3.3V
Note 1: Typical values are for when Ta
25C and Vcc
3.0 V unless otherwise noted.
Note 2: Icc measurement conditions (Normal, Slow): All functions are operating; output pins are open and input pins are fixed.
91CW12A-16
2003-05-21
TMP91CW12A
4.3 AC Characteristics
(1) Vcc No. Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 tFPH tAL tLA tLL tLC tCLR tCLW tACL tACH tCAR tCAW tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tAP
3.0 V
10% Variable Parameter Min Max
31250 6 16 20 14 10 10 23 26 13 13 3.0x 3.5x 2.0x 2.0x 0 x 1.5x
WR Rise
1 WAIT n Mode 1 WAIT n Mode 1 WAIT n Mode
fFPH Min
37.0 12 2 17 4 8 27 14 29 5 24 38 41 30 59 0 22 40 20 12
27 MHz Max
Unit
ns ns ns ns ns ns ns ns ns ns ns
fFPH Period ( x) A0 to A15 Vaild ALE Fall ALE Fall
RD Rise WR Rise
37.0 ALE Fall 0.5x 0.5x x 0.5x 0.5x x x 1.5x 0.5x x
A0 to A15 Hold
RD / WR Fall
ALE High Width ALE Rise ALE Rise
RD / WR Fall RD / WR Fall
A0 to A15 Valid A0 to A23 Valid
RD Rise WR Rise
A0 to A23 Hold A0 to A23 Hold D0 to D15 Input D0 to D15 Input
A0 to A15 Valid A0 to A23 Valid
RD Fall RD Low Width RD Rise RD Rise
73 88 44
ns ns ns ns ns ns ns ns ns
D0 to D15 Input 15 15 15 35 25 D0 to A15 Hold A0 to A15 Output
WR Low Width
D0 to D15 Valid
WR Rise
1.5x x
D0 to D15 Hold
WAIT Input WAIT Input WAIT Hold
A0 to A23 Valid A0 to A15 Valid
RD / WR Fall
3.5x 3.0x 2.0x 0 3.5x 3.5x 3.5x
60 50 74 89 129 80
69 61
ns ns ns
A0 to A23 Valid A0 to A23 Valid A0 to A23 Valid
Port Input Port Hold Port Valid
40 209
ns ns ns
AC Measuring Conditions Output Level: High 0.7 Vcc, Low 0.3 Vcc, CL Input Level: High 0.9 Vcc, Low 0.1 Vcc
50 pF
Note: x used in an expression shows a frequency for the clock fFPH selected by SYSCR1. The value of x changes according to whether a clock gear or a low-speed oscillator is selected. An example value is calculated for fc, with gear 1/fc (SYSCR1 0000).
91CW12A-17
2003-05-21
TMP91CW12A
(2) Vcc No. Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 tFPH tAL tLA tLL tLC tCLR tACW tACL TACH tCAR TCAW tADL tADH TRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tAP fFPH Period ( A0 to A15 ALE Fall ALE Fall
RD Rise WR Rise
2.0 V
10% Variable Parameter Min
x) ALE Fall A0 to A15 Hold
RD / WR Fall
fFPH Min
100 22 15 60 22 30 80 25 80 20 70
10 MHz Max
Max
31250
Unit
ns ns ns ns ns ns ns ns ns ns ns
100 0.5 x 0.5 x x 0.5x 0.5x x x 0.5x x 28 35 40 28 20 20 75 30 30
ALE High Width ALE Rise ALE Rise
RD / WR Fall RD / WR Fall
A0 to A15 Valid A0 to A23 Valid
RD Rise WR Rise
1.5x 70
A0 to A23 Hold A0 to A23 Hold D0 to D15 Input D0 to D15 Input
A0 to A15 Valid A0 to A23 Valid
RD Fall RD Low Width RD Rise RD Rise
3.0x 3.5x 2.0x 2.0x 0 x 1.5 x 1.5 x x 30 30 70 50 3.5x 3.0x 2.0x 0 3.5x 3.5x 3.5x 30
76 82 60 170 0 70 120 80 50 120 100 200 170 350 170
224 268 140
ns ns ns ns ns ns ns ns ns
D0 to D15 Input D0 to D15 Hold A0 to A15 Output
WR Rise
1WAIT n mode 1WAIT n mode 1WAIT n mode
WR Low Width
D0 to D15 Valid
WR Rise
D0 to D15 Hold
WAIT Input WAIT Input WAIT Hold
A0 to A23 Valid A0 to A15 Valid
RD / WR Fall
230 200
ns ns ns
A0 to A23 Valid A0 to A23 Valid A0 to A23 Valid
Port Input Port Hold Port Valid
180 520
ns ns ns
AC Measuring Conditions Output Level: High 0.7 Vcc, Low 0.3 Vcc, CL Input Level: High 0.9 Vcc, Low 0.1 Vcc
50 pF
Note: x used in an expression shows a frequency for the clock fFPH selected by SYSCR1. The value of x changes according to whether a clock gear or a low-speed oscillator is selected. An example value is calculated for fc, with gear 1/fc (SYSCR1 0000).
91CW12A-18
2003-05-21
TMP91CW12A
(3) Read Cycle
tFPH fFPH
A0 to A23
CS0 to CS3
R/ W
tAWH tAWL
tCW
WAIT
tAPH Port input tAPH2 tADH
RD
tCAR tRR tRAE tHR D0 to D15
tACH tACL tLC
tRD tADL
AD0 to AD15
A0 to A15 tAL tLA
tCLR
ALE
tLL
91CW12A-19
2003-05-21
TMP91CW12A
(4) Write Cycle
fFPH
A0 to 23
CS0 to CS3
R/ W
WAIT
tAP Port Output tCAW
WR , HWR
tWW tDW tWD
AD0 to 15
A0 to 15
D0 to 15 tCLW
ALE
91CW12A-20
2003-05-21
TMP91CW12A
4.4 AD Conversion Characteristics
AVcc Parameter
Analog Reference Voltage ( ) Analog Reference Voltage ( ) Analog Input Voltage Range Analog Current for Analog Reference Voltage 1 0
Vcc, AVss Max
Vcc Vcc Vss 0.2 V Vss VREFH
Vss Unit
V
Symbol
VREFH VREFL VAIN
Condition
VCC VCC VCC VCC VCC 3V 2V 3V 2V 10% 10% 10% 10%
Min
VCC 0.2 V VCC VSS VSS VREFL
Typ.
Vcc Vcc Vss Vss
3V 2V
10% 10%
0.94 0.65 0.02 1.0 1.0
1.20 mA 0.90 5.0 4.0 4.0 LSB A
IREF (VREFL
0V)
VCC VCC VCC VCC
1.8 V to 3.3 V 3V 2V 10% 10%
Error (not including quantizing errors)
Note 1: 1 LSB
(VREFH
VREFL)/1024 [V] 4 MHz.
Note 2: The operation above is guaranteed for fFPH
Note 3: The value for ICC includes the current which flows through the AVCC pin.
91CW12A-21
2003-05-21
TMP91CW12A
4.5 Serial Channel Timing (I/O Interface Mode)
(1) SCLK Input Mode Parameter
SCLK Period Output Data SCLK Rising/Falling Edge* Vcc 3V 10% Vcc 2V 10%
Symbol
tSCY
Variable Min
16X tSCY/2 4X 4X 2X 10 tSCY 0 0 110 180 0
10 MHz Max Min
1.6 290 220 1000 310 1600 0
27 MHz Min
0.59 38
Max
Max
Unit
s ns ns
tOSS tSCY/2 tOHS tHSR tSRD tRDS tSCY/2 3X
SCLK Rising/Falling Edge* Output Data Hold SCLK Rising/Falling Edge* Input Data Hold SCLK Rising/Falling Edge* Valid Data Input Valid Data Input SCLK Rising/Falling Edge*
370 121 592 0
ns ns ns ns
(2) SCLK Output Mode Parameter
SCLK Period Output Data SCLK Rising /Falling Edge*
Symbol
tSCY tOSS tOHS tHSR tSRD tRDS
Variable Min
16X tSCY/2 tSCY/2 0 tSCY 1X 180 1X 180 40 40
10 MHz Max Min
1.6 760 760 0 1320 280
27 MHz Min
0.59 256 256 0 375 217
Max
819
Max
303
Unit
s ns ns ns ns ns
8192X
SCLK Rising/Falling Edge* Output Data Hold SCLK Rising/Falling Edge* Input Data Hold SCLK Rising/Falling Edge* Valid Data Input Valid Data Input SCLK Rising/Falling Edge*
Note:
SCLK Rinsing/Falling Edge: The rising edge is used in SCLK Rising Mode. The falling edge is used in SCLK Falling Mode. 27 MHz and 10 MHz values are calculated from tSCY 16X case.
tSCY
SCLK Output Mode/ Input Mode SCLK (Input Mode) OUTPUT DATA TxD
tOSS 0
tOHS 1 tRDS tSRD tHSR 1 Valid 2 Valid 3 Valid 2 3
INPUT DATA RxD
0 Valid
91CW12A-22
2003-05-21
TMP91CW12A
4.6 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1)
Parameter
Clock Perild Clock Low Level Width Clock High Level Width
Symbol
tVCK tVCKL tVCKH
Variable Min
8X 4X 4X 100 40 40
10 MHz Min
900 440 440
27 MHz Min
396 188 188
Max
Max
Max
Unit
ns ns ns
4.7 Interrupt and Capture
(1) NMI , INT0 to INT4 Interrupts Symbol
tINTAL tINTAH
Parameter
NMI , INT0 to INT4 Low level width NMI , INT0 to INT4 High level width
Variable Min
4X 4X 40 40
10 MHz Min
440 440
27 MHz Min
188 188
Unit
ns ns
Max
Max
Max
(2) INT5 to INT8 Interrupts, Capture The INT5 to INT8 input width depends on the system clock and prescaler clock settings. System Clock Selected
0 (fc) 1 (fs)
tINTBH tINTBL Prescaler Clock (INT5 to INT8 Low level Width) (INT5 to INT8 High Level Width) Unit Selected Min Min Min Min
00 (fFPH) 10 (fc/16) 00 (fFPH) 8X 128Xc 8X 100 0.1 0.1 396 4.8 244.3 8X 128Xc 8X 100 0.1 0.1 396 4.8 244.3 ns s
Note: Xc
Period of Clock fc
4.8 SCOUT Pin AC Characteristics
Parameter
Low level Width High level Width
Symbol
tSCH tSCL
Variable Min
0.5T 0.5T 0.5T 0.5T 13 25 13 25
10 MHz Min
37 25 37 25
27 MHz Min
5 5
Max
Max
Max
Condition
Vcc Vcc 2.7 V 2.7 V
Unit
ns ns
Vcc < 2.7 V Vcc < 2.7 V
Note: T
Period of SCOUT
Measrement Condition Output Level: High 0.7 Vcc/Low 0.3 Vcc, CL
tSCH tSCL SCOUT
10pF
91CW12A-23
2003-05-21
TMP91CW12A
4.9 Bus Request/Bus Acknowledge
BUSRQ
(Note 1)
BUSAK
tCBAL tBA
AD0 to AD15 A0 to A23, RD , WR
tABA
(Note 2)
(Note 2)
CS0 to CS3 , R/ W , HWR
ALE
Paramter
Output Buffer Off to BUSAK Low
BUSAK High to Output Buffer On
Symbol
tABA tBAA
Variable Min
0 0 0 0
fFPH Min
0 0 0 0
10 MHz Max
80 300 80 300
fFPH Min
0 0 0 0
27 MHz Max
80 300 80 300
Condition
Vcc Vcc 2.7 V 2.7 V
Unit
Max
80 300 80 300
ns ns
Vcc < 2.7 V Vcc < 2.7 V
Note 1: Even if the BUSRQ Signal goes Low, the bus will not be released while the WAIT signal is Low. The bus will only be released when BUSRQ goes Low while WAIT is High. Note 2: This line shows only that the output buffer is in the Off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the Active and Non-Active states by the internal signal.
91CW12A-24
2003-05-21
TMP91CW12A
4.10 Recommended Oscillation Circuit
The TMP91CW12AF has been evaluated by the following resonator manufacturer. The evaluation results are shown below for your information. Note: The load capacitance of the oscillation terminal is the sum of the load capacitances of C1 and C2 to be connected and the stray capacitance on the board. Even if the ratings of C1 and C2 are used, the load capacitance varies with each board and the oscillator may malfunction. Therefore, when designing a board, make the pattern around the oscillation circuit shortest. It is recommended that final evaluation of the resonator be performed on the board.
(1) Examples of resonator connection
X1 X2 XT1 XT2
Rd
Rd
C1
C2
C1
C2
Figure 4.10.1 High-frequency Oscillator Connection
Figure 4.10.2 Low-frequency Oscillator Connection
(2) Recommended ceramic resonators for the TMP91CW12AF: Murata Manufacturing Co., Ltd.
Ta 40 to 85C
Item
Oscillation Recommended frequency resonator [MHz]
2.0 2.5 CSA2.00MG042 CST2.00MG042 CSA2.50MG042 CST2.50MGW042 CSA4.00MG040 CST4.00MGW040 CSTS0400MG06 CSA4.00MGU040 CST4.00MGWU040 CSA6.75MTZ040 CST6.75MTW040 CSTS0675MG06 CSA6.75MTZ093 CST6.75MTW093 CSA10.0MTZ CST10.0MTW CSA10.0MTZ093 CST10.0MTW093 CSA12.5MTZ CST12.5MTW CSA20.00MXZ040 CSA27.00MXZ040 CST27.00MXW040
Recommended rating C1[pF]
100 (100) 100 (100) 100 (100) (47) 100 (100) 100 (100) (47) 30 (30) 30 (30) 30 (30) 30 (30) 7 5 (5)
C2[pF]
100 (100) 100 (100) 100 (100) (47) 100 (100) 100 (100) (47) 30 (30) 30 (30) 30 (30) 30 (30) 7 5 (5)
Rd[k
]
VCC[V]
Remarks
1.8 to 2.2
2.7 to 3.3 1.8 to 2.2 2.7 to 3.3 0 1.8 to 2.2 2.7 to 3.3 1.8 to 2.2
4.0
High-frequ ency oscillator
6.75
10.0
12.5 20.0 27.0
2.7 to 3.3
The values enclosed in brackets in the C1 and C2 columns apply to the condenser built-in type. The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL; http://www.murata.co.jp/search/index.html
91CW12A-25
2003-05-21
TMP91CW12A
91CW12A-26
2003-05-21

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